View DS2746_2263971.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 15 rev: 122706 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . general description the DS2746 provides system-side battery capacity monitoring in cost-sensitive applications. voltage, bidirectional current, and accumulated current measurement data is provi ded to the host processor over a 2-wire interface. offset bias and offset blanking features greatly enhance the accuracy of the coulomb counter. in addition, the DS2746 has two auxiliary a/d inputs to sample the pack identification resistor, ther mistor, or other voltage source. the results are reported as a ratiometric fraction of the supply voltage eliminating error related to the supply. the DS2746 reduces the total power consumption of the measurement circuit by enabling the resistor dividers, through the v out pin, only while measurements are made. when the system is inactive, a low power sleep mode reduces current consumption while maintaining the coulomb count. the tiny 3mm 3mm tdfn package consumes only 9mm 2 of pcb space. applications 2.5g/3g wireless handsets pda/smartphones digital still and video cameras handheld computers and terminals typical operating circuit features ? 14-bit bidirectional current measurement - 6.25 v lsb, 51.2mv dynamic range - 416.7 a lsb, 3.4a range (r sns = 15m ) ? current accumulation register resolution - 6.25 vhr lsb, 409.6mvh range - 417 ahr lsb, 27.31ah range ? 11-bit battery voltage measurement - 2.44mv lsb, 0v to 4.997v input range - 10mv accuracy at 3.6v input ? two 11-bit aux input voltage measurements - ratiometric inputs eliminate supply error - vout drives dividers, reduces power - 8 lsb accuracy ? low power consumption: - active current: 70 a typical, 100 a max - sleep current: 1 a typical, 3 a max ordering information part temp range pin-package DS2746g+ -40oc to +85oc 10-pin 3 mm 3mm tdfn DS2746g+t&r -40oc to +85oc DS2746g+ in tape- and-reel + denotes lead-free package. pin configuration DS2746 low-cost 2-wire battery monito r with ratiometric a/d inputs www.maxim-ic.com top view 3mm 3mm tdfn
DS2746 low-cost 2-wire battery monitor 2 of 15 absolute maximum ratings voltage range on any pin relative to ground -0.3v to +6v operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature see ipc/jedecj-std-020a stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rating condi tions for extended periods may affect device reliability. recommended dc oper ating conditions (v cc = 2.5v to 5.5v, t a = -20c to +70c.) parameter symbol conditions min typ max units supply voltage v dd (note 1) +2.5 +5.5 v data i/o pins scl, sda (note 1) -0.3 +5.5 v programmable i/o pin pio (note 1) -0.3 +5.5 v v in , ain0, ain1 pin v in , ain0, ain1 (note 1) -0.3 v dd + 0.3 v dc electrical characteristics (v cc = 2.5v to 4.5v, t a = -20c to +70c.) parameter symbol conditions min typ max units 70 100 active current i active v dd = 5.5v 105 a v dd = 2.0v, scl, sda = vss 0.5 1.0 sleep-mode current i sleep scl, sda = vss 1 3 a current resolution i lsb 6.25 v current full-scale magnitude i fs (note 1) 51.2 mv current offset i oerr (note 2) - 12.5 + 12.5 v current gain error i gerr (note 11) - 1.5 +1.5 % of reading v dd = 3.6v at +25c - 1 + 1 t a = 0 c to +70 c - 2 + 2 % timebase accuracy t err t a = -20 c to +70 c - 3 + 3 v dd = v in = 3.6v - 10 + 10 voltage error v gerr - 20 + 20 mv input resistance v in , ain0, ain1 r in 15 m ? ain0, ain1 error 2.5v v dd 4.1v, v ain0,1 v dd , (note 10) - 8 + 8 lsb ain0, ain1 error 4.1v < v dd 4.2v, v ain0,1 0.95v dd , (note 10) - 8 + 8 lsb ain0, ain1 error 4.2v < v dd 4.5v, v ain0,1 0.75v dd , (note 10) - 8 + 8 lsb v out output drive i o = 1ma v dd -0.1 v v out precharge time t pre v odis bit = 0 13.3 14.2 ms
DS2746 low-cost 2-wire battery monitor 3 of 15 input logic high: scl, sda v ih (note 1) 1.5 v input logic low: scl, sda v il (note 1) 0.6 v output logic low: sda v ol i ol = 4ma, (note 1) 0.4 v pulldown current: scl, sda i pd v dd = 4.2v, v pin = 0.4v 0.2 a input capacitance: scl, sda c bus 50 pf bus low timeout t sleep (note 3) 1.5 2.2 s dc electrical characterist ics: 2-wire interface (v cc = 2.5v to 5.5v, t a = -20c to +70c.) parameter symbol conditions min typ max units scl clock frequency f scl (note 4) 0 400 khz bus free time between a stop and start condition t buf 1.3 s hold time (repeated) start condition t hd:sta (note 5) 0.6 s low period of scl clock t low 1.3 s high period of scl clock t high 0.6 s setup time for a repeated start condition t su:sta 0.6 s data hold time t hd:dat (note 6, 7) 0 0.9 s data setup time t su:dat (note 6) 100 ns rise time of both sda and scl signals t r 20 + 0.1c b 300 ns fall time of both sda and scl signals t f 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 s spike pulse widths suppressed by input filter t sp (note 8) 0 50 ns capacitive load for each bus line c b (note 9) 400 pf scl, sda input capacitance c bin 60 pf note 1: all voltages are referenced to v ss . note 2: offset specified after auto-calibration cycle and current offset bias register = 0x00. note 3: the DS2746 enters the sleep mode 1.5s to 2.2s after ( scl < v il .) and ( sda < v il ). note 4: timing must be fast enough to prevent the DS2746 from entering sleep mode due to bus low for period > t sleep . note 5: f scl must meet the minimum clock lo w time plus the rise/fall times. note 6: the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 7: this device internally provides a hold time of at least 100ns for the sda signal (referr ed to the vihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 8: filters on sda and scl suppress noise spikes at the input buffers and delay the sampling instant. note 9: c b ? total capacitance of one bus line in pf. note 10: the 8lsb spec is valid when this equation is satisfied: (v ainx + 2v out ) (12.9v - (t a - 25 c)10mv/ c). note 11: accuracy specification valid for v ss - sns 2.5mv, below which offset error is dominant.
DS2746 low-cost 2-wire battery monitor 4 of 15 figure 1. 2-wire bus timing diagram pin description pin name function 1 ain1 aux voltage input number 1. 2 ain0 aux voltage input number 0. 3 scl serial clock input. input only 2-wire clock line. connect this pin to the clock signal of the 2-wire interface. this pin has a 0.2 a typical pulldown to sense disconnection. 4 sda serial data input / output. open drain 2-wire data line. connect this pin to the data signal of the 2-wire interface. this pin has a 0.2a typical pulldown to sense disconnection. 5 sns current-sense input. connect to the handset side of the sense resistor. 6 v ss device ground. connect to the battery side of the sense resistor. 7 ctg connect to ground. connect to the battery side of the sense resistor. 8 v out voltage out. supply for aux input voltage measurement dividers. connect to high side of resistor divider circuits. 9 v in battery voltage input. the voltage of the cell pack is measured through this pin. 10 v dd power-supply input. 2.5v to 5.5v input range. connect to system power through a decoupling network. pad pad exposed pad. connect to v ss.
DS2746 low-cost 2-wire battery monitor 5 of 15 figure 2. block diagram detailed description the DS2746 operates either in active mode where cell vo ltage, system current, and auxiliary inputs are monitored, or in a low power sleep mode to conserve energy when the system is idle. while in active mode, the DS2746 contantly measures current flow through an external se nse resistor. each current measurement is reported with sign and magnitude in a two-byte current register. offset bias and offset blanking features remove offset error from the current a/d to improve measurement accuracy. each current measurement is integrated into the accumulated current register (acr) to ma intain a sum of all charge entering and exiting the cell. the DS2746 has two auxiliary inputs to allow voltage samp ling of resistor divider circuits. these can be used to measure a thermistor or an id resistor located inside the battery pack. the v out output provides the pullup voltage for the resistor divider networks. the DS2746 disables v out after measuring the auxiliary inputs to re duce power use by the measurement system. v out operation can be disabled through software to further reduce power consumption when the auxiliary inputs are not in use. a dedicated voltage a/d measures voltage of the cell and the auxiliary inputs. a mux on the input to the a/d cycles through the v in , ain0, and ain1 pins repeatedly in that order. an internal reference is used to measure v in voltage. ain0 and ain1 are measured as a percentage of v out . this ratiometric measurement of the auxiliary inputs prevents noise in the supply from affecting accuracy of the readings the DS2746 measurements can be used directly to provid e accurate fuel gauging in typical use conditions, or along with fuelpack? algorithms to form a complete and accurate solution for estimating remaining capacity over wide temperature and operating conditions. through its 2-wire interface, the DS2746 allows a host system read/write access to the status/configuration register and measurement regi sters. if sleep mode operation is enabled, holding both interface lines low forces the DS2746 into a low power sleep mode where a/d measurem ents are paused and the acr register is maintained. fuelpack is a trademark of dallas semiconductor.
DS2746 low-cost 2-wire battery monitor 6 of 15 figure 3. application example power modes the DS2746 operates in one of two power modes: active and sleep. while in active mode, the DS2746 operates as a high-precision battery monitor with voltage, auxiliary inputs, current and accumulated current measurements acquired continuously and the resulting values updated in the measurement registers. read and write access is allowed to all registers. in sleep mode, the DS2746 operat es in a low-power mode with no measurement activity. the DS2746 operating mo de transitions from sleep to active when: ( scl > v ih ) or ( sda > v ih ) the DS2746 operating mo de transitions from active to sleep when: smod = 1 and [ ( scl < v il ) and ( sda < v il ) ] for t sleep caution : if smod = 1, a pull-up resistor is required on scl and sda in order to ensure that the DS2746 transitions from sleep to active mode when the battery is charged. if t he bus is not pull ed up, the DS2746 remains in sleep and cannot ac cumulate the charge current. measurement sequence the DS2746 uses seperate a/d converters to make voltage and current measurem ents. each a/d converter operates completely independent of t he other, allowing measurements of voltage and current to be made in parallel. current measurements are made at a resolution of 13 bits plus sign bit. the current register is updated every 878ms with the average for that time period. all voltage measurements are made at a resolution of 11 bi ts plus sign bit. the DS2746 continouly cycles through measuring v in , ain0, and ain1 in that order. voltage measurem ent of each input requires 220ms to complete. a full sequence of voltage measurements requires 660ms to complete. v out is active for a precharge time of t pre before the ain0 measurement time occurs. the v out pin is enabled during the entire ain0 and ain1 measurement sequence as long as the v odis (v out disable) bit is cleared. see figure 4.
DS2746 low-cost 2-wire battery monitor 7 of 15 figure 4. measurement timing voltage measurement battery voltage is measured at the v in input with respect to v ss over a range of 0v to 4.997v and with a resolution of 2.44mv. the result is updated ev ery 660ms with the average voltage over the last 220ms and placed in the voltage register in two?s compliment form. voltages abov e the maximum register value are reported as 7fffh. figure 5. voltage register format msb?address 0ch lsb?address 0dh s 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x msb lsb msb lsb ?s?: sign bit(s), ?x?: reserved units: 2.44mv the input impedance of v in is sufficiently large (>15m ) to be connected to a high impedance voltage divider in order to support multiple cell applications. the pack volt age should be divided by the number of series cells to present a single cell average voltage to the v in input.
DS2746 low-cost 2-wire battery monitor 8 of 15 auxilary input measurements the DS2746 allows for measuring two auxiliary meas urement inputs, ain0 and ain1, with respect to v ss . these inputs are designed for measuring resistor ratios, particular ly useful for measuring thermistor or pack identification resistors. at a time of t pre prior to the beginning of a measurement cycle on ain0 or ain1, the v out pin puts out a reference voltage in order to drive a resistive divider form ed by a known resistor val ue, and the unknown resistance to be measured. making these measurements ratiometric with respect to v out removes reference tolerance from the error calculations. each auxiliary input measurement is updated every 660ms with the average voltage over the 220ms conversion period and placed in the ain0 and ain1 registers in two?s complement form. the input impedances of ain0 and ain1 are sufficiently large (>15m ) to be connected to a wide range of voltage divider resistances. figure 6. auxiliary input registers format ain0 msb?address 08h lsb?address 09h s 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x msb lsb msb lsb ?s?: sign bit, ?x?: reserved units: 1lsb = v vout * 1/2047 ain1 msb?address 0ah lsb?address 0bh s 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x x x msb lsb msb lsb ?s?: sign bit, ?x?: reserved units: 1lsb = v vout * 1/2047 current measurement in the active mode of operation, the DS2746 continually measures the current fl ow into and out of the battery by measuring the voltage drop across a low-value current-sense resistor, r sns , connected between the sns and v ss pins. the voltage sense range between sns and v ss is 51.2mv. note that positive current values occur when v sns is less than v ss , and negative current values occur when v sns is greater than v ss . peak signal amplitudes up to 102mv are allowed at the input as long as the conti nuous or average signal level does not exceed 51.2mv over the conversion period. the adc samples the input different ially and updates the current r egister at the completion of each conversion. the result is updated every 878m s with the average voltage and placed in the current register in two?s compliment form. the current measurement register format is shown in figure 7 and specifications for several different sense resistor options are shown in tables 1 and 2. charge currents above the maximum register value are reported at the maximum value (7 fffh = +51.2mv). discharge currents below the minimum register value are reported at the minimum value (8000h = -51.2mv). figure 7. current register formats msb?address 0eh lsb?address 0fh s 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x msb lsb msb lsb ?s?: sign bit units: 2 0 = 6.25 v/rsns
DS2746 low-cost 2-wire battery monitor 9 of 15 table 1. current resolution for various rsns values current resolution (1 lsb) r sns v ss - v sns 20m 15m 10m 5m 6.25 v 312.5a 416.7a 625a 1.25ma table 2. current range for various rsns values current input range r sns v ss - v sns 20m 15m 10m 5m 51.2mv 2.56a 3. 41a 5.12a 10.24a every 1024th conversion, the adc measures its input offset to facilitate offset correction. offset correction occurs approximately once per hour. the resulting correction fa ctor is applied to the subsequent 1023 measurements. during the offset correction conversion, the adc does not measure the sns to v ss signal. a maximum error of 1/1024 in the accumulated current register (acr) is po ssible, however, to reduce the error, the current measurement just prior to the offset conversion is displayed in the current register and is substituted for the dropped current measurement in the curr ent accumulation process. the error due to offset correction is typically much less than 1/1024 of the expected reading. current accumulation the accumulated current register (acr) serves as an up/ down counter holding a running count of charge stored in the battery. current measurement results, plus a programma ble bias value are internally summed, or accumulated, at the completion of each current measurement conversion period with the results displayed in the acr. the acr has a range of 0mvh to + 409.6mvh with an lsb of 6.25 vh . additional registers hold fractional results of each accumulation, however, these bits are not user accessib le. the acr count clamps at ffffh when accumulating charge values and at 0000h when accumulating discharge values. read and write access is allowed to the acr. whenever t he acr is written, fractional accumulation results are cleared. a write to the acr also forces the adc to measure its offset and update the offset correction factor. current measurement and accumulation resume (using t he new offset correction) wi th the second conversion following the write to the acr. figure 8 describes the acr address, format, and resolution. table 3 shows the acr?s dynamic range for several different sense resistor options. figure 8. accumulated current register format msb?address 10h lsb?address 11h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb msb lsb ?s?: sign bit units: 6.25 vh/rsns
DS2746 low-cost 2-wire battery monitor 10 of 15 table 3. accumulated current ra nge for various rsns values acr range r sns v ss - v sns 20m 15m 10m 5m 409.6mvh 20.48ah 27. 31ah 40.96ah 81.92ah current offset bias the current offset bias register (cobr) allows a programmable offset value to be added to raw current measurements. the result of the raw current measurement plus the cobr value is displayed as the current measurement result in the current register, and is used for current accumulation. the cobr value can be used to correct for a static offset error, or can be used to int entionally skew the current resu lts and therefore the current accumulation. read and write access is allowed to cobr. whenever t he cobr is written, the new value is applied to all subsequent current measurements. cobr can be programmed in 1.56 v steps to any value between +198 v and -200 v. the cobr value is stored as a two?s complement va lue in volatile memory, and must be initialized via the interface on power-up. figure 9 describes the cobr address, format, and resolution. figure 9. current offset bias register format address 61h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb ?s?: sign bit units: 1.56 v/rsns current blanking the current blanking feature modifies current measurement result prior to being accumulated in the acr. current blanking occurs conditionally when a current measurem ent (raw current + cobr) falls in one of two defined ranges. the first range prevents charge currents less than 100 v/r sns from being accumulated. the second range prevents discharge currents less than 25 v/r sns in magnitude from being accumulated. charge current blanking is always performed, however, discharge current blank ing must be enabled by setting the nben bit in the status/config register. see the register description for additional information. accumulation bias the accumulation bias register (abr) allows a programmabl e offset value to be added to the current accumulation process. the new acr value results from the addition of t he current register value plus abr plus the previous acr value. abr can be used to intent ionally skew the current accumulation to estimate system stand-by currents that are too small to measure. abr value is not subject to the current blanking thresholds. read and write access is allowed to the abr. whenever the abr is written, the new value is applied to all subsequent current measurements. abr can be set to any value between +193.75 v and -200 v in 6.25 v steps. the abr value is stored as a two?s complement value in volatile memory, and must be initialized via the interface on power-up. the lower two bits of the abr register hav e no effect on the data. figure 10 describes the abr address, format, and resolution.
DS2746 low-cost 2-wire battery monitor 11 of 15 figure 10. accumulation bias register format address 62h s 2 4 2 3 2 2 2 1 2 0 x x msb lsb ?s?: sign bit units: 6.25 vh/rsns memory the DS2746 has memory space with registers for instrum entation, status, and control. when the msb of a two- byte register is read, both the msb and lsb are latc hed and held for the duration of the read data command to prevent updates during the read and ensure synchronization between the two register bytes. for consistent results, always read the msb and the lsb of a two-byte regi ster during the same read data command sequence. table 4. memory map address (hex) description read/write por default 00 reserved ? 01 status/config register r/w x1110x00b 02 to 07 reserved ? 08 auxiliary input 0 register msb r 00h 09 auxiliary input 0 register lsb r 00h 0a auxiliary input 1 register msb r 00h 0b auxiliary input 1 register lsb r 00h 0c voltage register msb r 00h 0d voltage register lsb r 00h 0e current register msb r 00h 0f current register lsb r 00h 10 accumulated current register msb r/w undefined 11 accumulated current register lsb r/w undefined 12 to 60 reserved ? 61 offset bias register r/w 00h 62 accumulation bias register r/w 00h 63 to ff reserved ?
DS2746 low-cost 2-wire battery monitor 12 of 15 status/config register the status/config register is read/write with individual bi ts designated as read only. bit values indicate status as well as program or select device functionality. figure 11. status/conf ig register format address 01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x porf smod nben vodis x ain1 ain0 x ? reserved. porf ? the power-on-reset flag is set to indicate initial power-up. porf is not cleared internally. the user must write this flag value to a 0 in order to use it to indicate subsequent power-up events. if porf indicates a power-on-reset, the acr could be misaligned with the actual battery state of charge. the system can request a charge to full in order to synchronize the acr with th e battery charge state. po rf is read/write-to-zero. smod ? sleep mode enable. a value of 1 allows the DS2746 to enter slee p mode when scl and sda are low for t sleep . a value of 0 disables the transition to sl eep mode. the power-up default is smod = 1. nben ? negative blanking enable. a value of 1 enables blan king of negative current values up to 25v. a value of 0 disables blanking of negative curren ts. the power-up default is nben = 1. v odis ? v out disable. when set to 0 this output is driven t pre before the ain0 conversion begins, and disabled after the ain1 conversion ends. the power-up default is v odis = 0, a value of 1 disables the v out output. ain1 ? ain1 conversion valid. this read only bit indicates that the v out output was enabled, and a conversion has occurred on the ain1 pin. when using the v odis bit, before reading the ain1 register s, read the ain1 bit. only once the ain1 bit is set, should the ain1 register be read. ain0 ? ain0 conversion valid. this read only bit indicates that the v out output was enabled, and a conversion has occurred on the ain0 pin. when using the v odis bit, before reading the ain0 register s, read the ain0 bit. only once the ain0 bit is set, should the ain0 register be read. 2-wire bus system the 2-wire bus system supports operation as a slav e-only device in a single or multislave, and single or multimaster system. the 2-wire interface consists of a se rial data line (sda) and serial clock line (scl). sda and scl provide bidirectional communication between the ds27 46 slave device and a master device at speeds up to 400 khz. the DS2746?s sda pin operates bidirectionally, that is, when the DS2746 re ceives data, sda operates as an input, and when the DS2746 returns data, sda operate s as an open drain output, with the host system providing a resistive pullup. the ds27 46 always operates as a slave devic e, receiving and transmitting data under the control of a master device. the master initiates all transactions on the bus and generates the scl signal as well as the start and stop bits which begin and end each transaction. bit transfer one data bit is transferred during each scl clock cycle, with the cycle defined by scl transitioning low-to-high and then high-to-low. the sda logic level must remain st able during the high period of the scl clock pulse. any change in sda when scl is high is interpreted as a start or stop control signal.
DS2746 low-cost 2-wire battery monitor 13 of 15 bus idle the bus is defined to be idle, or not busy, when no master device has control. both sda and scl remain high when the bus is idle. the stop condition is the prop er method to return the bus to the idle state. start and stop conditions the master initiates transactions with a start condition (s), by forcing a high-to-low transition on sda while scl is high. the master terminates a transaction with a stop condition (p), a low-to-high transition on sda while scl is high. a repeated start condition (sr) can be used in place of a stop then star t sequence to terminate one transaction and begin another without returning the bu s to the idle state. in multimaster systems, a repeated start allows the master to retain control of the bus. the start and stop conditions are the only bus activities in which the sda transitions when scl is high. acknowledge bits each byte of a data transfer is acknowledged with an ac knowledge bit (a) or a no acknowledge bit (n). both the master and the DS2746 slave generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-relat ed clock pulse (ninth pulse) and keep it low until scl returns low. to generate a no acknowledge (also called n ak), the receiver releases sda before the rising edge of the acknowledge-related clock pulse an d leaves sda high until scl returns lo w. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsu ccessful data transfer can oc cur if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should re- attempt communication. data order a byte of data consists of 8 bits ordered most significant bit (msb) first. the least significant bit (lsb) of each byte is followed by the acknowledge bit. DS2746 registers composed of multibyte values are ordered most significant byte (msb) first. the msb of multibyte register s is stored on even data memory addresses. slave address a bus master initiates communication with a slave dev ice by issuing a start condition followed by a slave address (saddr) and the read/write (r /w) bit. when the bus is idle, the DS2746 continuously monitors for a start condition followed by its slave address. when the DS2746 receives a slave addr ess that matches its slave address, it responds with an acknowledge bit during t he clock period following the r/w bit. the 7-bit slave address is fixed. DS2746 slave address 0110110 read/write bit the r/w bit following the slave address determines the data direction of subsequent byte s in the transfer. r/w = 0 selects a write transaction, with the following bytes being wri tten by the master to the sl ave. r/w = 1 selects a read transaction, with the following bytes being read from the stave by the master. bus timing the DS2746 is compatible with any bus timing up to 400khz. no special configuration is required to operate at any speed. 2-wire command protocols the command protocols involve several tr ansaction formats. the simplest format consists of the master writing the start bit, slave address, r/w bit, and then monitoring the acknowledge bit for presence of the DS2746. more complex formats such as the write data, read data and function command protocols write data, read data and execute device specific operations. all bytes in each co mmand format require the slave or host to return an acknowledge bit before continuing with the next byte. each function command definition outlines the required transaction format. the following key applies to the transaction formats.
DS2746 low-cost 2-wire battery monitor 14 of 15 table 5. 2-wire protocol key key description key description s start bit sr repeated start saddr slave address (7-bit) w r/w bit = 0 fcmd function command byte r r/w bit = 1 maddr memory address byte p stop bit data data byte written by master data data byte returned by slave a acknowledge bit - master a acknowledge bit - slave n no acknowledge - master n no acknowledge - slave basic transaction formats write: s saddr w a maddr a data0 a p a write transaction transfers one or more data bytes to the DS2746. the data transfer begins at the memory address supplied in the maddr byte. contro l of the sda signal is retained by t he master throughout the transaction, except for the acknowledge cycles. read: s saddr w a maddr a sr saddr r a data0 n p write portion read portion a read transaction transfers one or more bytes from the DS2746. read transactions are composed of two parts, a write portion followed by a read portion, and is therefore inherently longer than a write transaction. the write portion communicates the starting point for the read operation. the read portion follows immediately, beginning with a repeated start, slave address with r/w set to a 1. c ontrol of sda is assumed by the DS2746 beginning with the slave address acknowledge cycle. control of the sda signal is retained by the DS2746 throughout the transaction, except for the acknowledge cycles. the master indicates the end of a read transaction by responding to the last byte it requires with a no acknowledge. this signals the DS2746 that control of sda is to remain with the master following the acknowledge clock. write data protocol the write data protocol is used to write to register and shadow ram data to the DS2746 starting at memory address maddr. data0 represents the data written to madd r, data1 represents the data written to maddr + 1 and datan represents the last data byte, wri tten to maddr + n. the master indicate s the end of a write transaction by sending a stop or repeated start after receiving the last acknowledge bit. s saddr w a maddr a data0 a data1 a ? datan a p the msb of the data to be stored at address maddr can be written immedi ately after the maddr byte is acknowledged. because the address is automatically incremented after the least significant bit (lsb) of each byte is received by the DS2746, the msb of t he data at address maddr + 1 is can be written immediately after the acknowledgement of the data at addres s maddr. if the bus master continues an auto-incremented write transaction beyond address 4fh, the DS2746 ignores the data. data is also ignored on writes to read-only addresses and reserved addresses, locked eeprom blocks as well as a write that auto increments to the function command register (address feh). incomplete bytes and bytes that are not acknowledged by the DS2746 are not written to memory. as noted in the memory section, writes to unlocked eeprom blocks modify the shadow ram only. read data protocol the read data protocol is used to read register a nd shadow ram data from the DS2746 starting at memory address specified by maddr. da ta0 represents the data byte in memory location maddr, data1 represents the data from maddr + 1 and datan represents th e last byte read by the master. s saddr w a maddr a sr saddr r a data0 a data1 a ? datan n p
DS2746 low-cost 2-wire battery monitor 15 of 15 data is returned beginning with the most significant bit (msb) of the data in maddr. because the address is automatically incremented after the least significant bit (lsb) of each byte is return ed, the msb of the data at address maddr + 1 is available to the host immediately a fter the acknowledgement of th e data at address maddr. if the bus master continues to read beyond address ffh, t he DS2746 outputs data values of ffh. addresses labeled ?reserved? in the memory map return undefined data. the bus master terminates the re ad transaction at any byte boundary by issuing a no acknowledge fo llowed by a stop or repeated start. package information (the package drawing(s) in this data s heet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .)

▲Up To Search▲

Price & Availability of DS2746

	To Download DS2746 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .